1. Field of the Invention
The present invention relates to a data split parallel shifter for splitting data in connection with a processing of a microprocessor and then executing a shifting operation. Further, the present invention relates to an adder/subtractor and, more particularly, an adder/subtractor employed in a processor for supporting mainly multimedia functions, etc.
2. Description of the Prior Art
In a processor module of a processor for executing data processing, as an approach for improving a data processing efficiency, there is a processing system in which data are split into a plurality of fields and then data in respective fields are processed in bulk. For example, 64-bit data is split into four 16-bit data and then four adding operations are executed at the same time according to an add command.
A[63:48] A[47:32] A[31:16] A[15:0] + + + + B[63:48] B[47:32] B[31:16] B[15:0] = = = = C[63:48] C[47:32] C[31:16] C[15:0]
This processing system can show its performance in the fields such as image processing, speech processing, etc. rather than existing scientific and technical computation, business processing computation, etc. These processings need a shifting process in addition to the arithmetic operations and the logical operation. Normally, as the shifting process, there are the logical shift in which 0 is filled in vacant locations caused by shift, and the arithmetic shift which executes the code extension. In order to enable the shifting process after the data is split into a plurality of fields, a switching process indicating which portion of the fields should be code-extended in conformity with split mode is requested. For example, the results derived when a 3-bit rightward arithmetic shift is applied to 32-Bit data in a 32 bit mode, a 16 bit.times.2 mode, and an 8 bit.times.4 mode respectively are given in the following.
 bit 31 bit 0 Original data 110 11011 001 10101 001 00100 100 10100 32 bit mode 111 11011 011 00110 101 00100 100 10010 16 bit .times. 2 mode 111 11011 011 00110 000 00100 100 10010 8 bit .times. 4 mode 111 11011 000 00110 000 00100 111 10010
Out of the above data, underlined portions are code extension portions. That is, the code extension is applied to the bit 31 in the 32-bit shift mode. In the 16 bit.times.2 mode, the code extension is applied to the bit 31 in upper 16 bits, while the code extension is applied to the bit 15 in lower 16 bits. In the 8 bit.times.4 mode, the bit 31 is extended in the bit range from the bit 31 to the bit 24, the bit 23 is extended in the bit range from the bit 23 to the bit 16, the bit 15 is extended in the bit range from the bit 15 to the bit 8, and the bit 7 is extended in the bit range from the bit 7 to the bit 0. In the logical shift, the above underlined portions are extended into 0.
Next, a configuration of the shifter will be explained hereunder. For clarification of explanation, the rightward shifting process will be explained.
To begin with, the normal shifter without a split function will be explained. A normal 32-bit rightward shifter is shown in FIG. 1. In FIG. 1, in the 32-bit shifter, bit shifters 101 to 105 for shifting the data by 1 bit, 2 bit, 4 bit, 8 bit, and 16 bit respectively are connected in a multistage fashion. Such bit shifters are constructed by a simple selector respectively. The 32-bit shifter is constructed by stacking these selectors in a multistage fashion. The 1-bit shifter 101 outputs data, which is located at the bit adjacent to the corresponding bit on the left side by one bit, out of the data supplied from the 2-bit shifter 102 when the shifting is executed, while the 1-bit shifter 101 outputs data located at the corresponding bit as it is when the shifting is not executed. A select signal indicating whether adjacent data should be output or the data should be output as it is can be generated based on the least significant bit of the signal indicating an amount of shift and the signal indicating the leftward/rightward shifting direction. More particularly, the 1-bit shifting is executed if 1 is set at the least significant bit, while the 1-bit shifting is not needed if 0 is set at the least significant bit and thus the data is output downward as it is. In the 2-bit shifter 102, either the data located on the left side by two bits in relation to the corresponding bit should be output or the data located at the corresponding bit should be output as it is can be selected. The select signal for the 2-bit shifter 102 is a value on the second least significant bit in the signal indicating the amount of shift. Depending upon that which shifters are to be operated in compliance with the amount-of-shift signal respectively, the shifting operation to achieve any amount of shift ranging from the 0 bit to 31 bit can be carried out. For instance, in the case of the 3-bit shifting, shift of the data is effected by the 1-bit shifter 101 and 2-bit shifter 102, nevertheless no shift of the data is effected by other shifters 103, 104, 105.
Unless the data is split into the fields, the code extension process can be implemented by extending either the leftmost value of the original data, if the arithmetic shift is applied, or b 0, if the logical shift is applied, by the bit number equal to the amount of shift from the most significant bit in respective shifters.
The data used in code extension consists of a control signal indicating which one of the arithmetic shift and the logical shift should be executed and actual code extension data, and such data can be generated previously in a code extension data generator. For example, there is no left-hand data to be fetched for the leftmost selector in the 1-bit shifter 101. However, if the code extension data supplied from the code extension data generator is inserted into the port, such leftmost selector can output the code extension data when one-bit shift is generated.
As shown in FIG. 2, the code extension data generator is constructed to comprise multiplexers 106 to 108 and logic gates 109 to 112, for example. In the arithmetic shift in which an arithmetic shift signal is at a high level, according to such configuration, the bit 31 of the original data is output as the code extension data for all 32 bits in the 32-bit shift mode. Then, in the 16 bit.times.2 mode, the bit 31 of the original data is output in the bit range of the upper bits 31 to 16 while the bit 15 of the original data is output in the bit range of the lower bits 15 to 0. Then, in the 8 bit.times.4 mode, the bit 31 of the original data is output in the bit range of the bits 31 to 24, the bit 23 of the original data is output in the bit range of the bits 23 to 16, the bit 15 of the original data is output in the bit range of the bits 15 to 8, and the bit 7 of the original data is output in the bit range of the bits 7 to 0. On the contrary, in the logical shift in which the arithmetic shift signal is at a low level, 0 is output to all bits as the code extension data.
In the event that the 16 bit.times.2 mode and the 8 bit.times.4 mode, described above, are added to the shifter shown in FIG. 1, it becomes an issue how the above code extension process should be carried out. As shown in FIG. 3, in order to add the code extension function, code extension selectors 113 for selecting either the code extension or the normal shift can be inserted between respective stages of the shifters 101 to 105 respectively.
In the 16bit.times.2 mode, the 16-bit shifter 105 controls all code extension selectors 113 to select the code extension. In the 8-bit shifter 104, the code extension selector 113 controls to select the code extension for the bits 15 to 8. Similarly, the 4-bit shifter 103 controls to select the code extension for the bits 15 to 12, the 2-bit shifter 102 controls to select the code extension for the bits 15 to 14, and the 1-bit shifter 101 controls to select the code extension for the bit 15.
In the 8 bit.times.4 mode, the 16-bit shifter 105 and the 8-bit shifter 104 controls all code extension selectors 113 to select the code extension. The 4-bit shifter 103 controls the code extension selectors 113 to select the code extension data for the bits 23 to 20, the bits 15 to 12, the bits 7 to 4. The 2-bit shifter 102 controls the code extension selectors 113 to select the code extension data for the bits 23 to 22, the bits 15 to 14, the bits 7 to 6. The 1-bit shifter 101 controls the code extension selectors 113 to select the code extension data for the bit 23, the bit 15, the bit 7.
In this way, if the code extension selectors 113 are inserted between the bit shifters respectively, the data can be split into a plurality of fields to achieve parallel shift. However, since such code extension selectors 113 are implemented by the selector which is the same in structure as the shifter, the circuit has twice the stage number of the normal shifter and thus a processing speed becomes very slow. In addition, the case where the code extension data generators are provided has been explained, but a delay time caused to generate the code extension data by the circuit is added to an entire delay time as it is in this case. As a method wherein the code extension data generator is not employed, the selector for selecting which data should be employed as the code extension data according to respective modes may be added to respective code extension selectors 113. In this case, increases in the delay of speed and the circuit scale are caused beyond the case where the code extension data generators are employed.
In the normal shifter, the data must be passed through five stages of the selectors for 32-bit shift. In order to improve the processing speed, such a circuit may be incorporated in place of the above that the process corresponding to those at two stages can be carried out at a time by employing the 4-input selector with a combined selecting function instead of the 2-input selector. For example, 1-bit shift and 2-bit shift are employed as inputs of the selector at one stage to enable selection of 3-bit leftward shift, 1-bit leftward shift, or no shift. However, if parallel shift function is added to such circuit, a circuit configuration of the shifter becomes complicated since the code extension selectors are increased three times every bit. In addition, in the barrel shifter which can effect both the leftward shift and the rightward shift, the code extension selectors are also increased two times and therefore a circuit configuration of the shifter becomes further difficult in respects of area and speed.
As described above, in the data split parallel shifter in the prior art in which split data are shifted in parallel respectively, if the code extension process is to be effected, such data split parallel shifter needs twice the selectors as many as the normal shifter without the code extension function, which yields increase in size and reduction in the processing speed. Further, since a time required for generating extension codes previously is added to the entire operating time of the shifter, the processing speed is lowered much more.
Next, the adder/subtractor in the prior art will be explained.
As the adder/subtractor in the prior art, there is a carry-select type adder/subtractor. The carry-select type is employed to accelerate the processing speed. More particularly, two adders each has respectively one of two way carries which are to be output from the lower bit adder as its constant respectively are prepared to obtain two way added results previously in upper bit calculation without waiting the carry from the lower bit adder, so that one of two way added results can be selected in the upper bit calculation based on the carry from the lower bit adder.
The carry-select type adder/subtractor in the prior art comprises a lower 16-bit adder, two adders for effecting upper 16-bit addition, and a carry/SUM selector for selecting one of added results from the two adders according to the carry supplied from the lower 16-bit adder to output it.
Besides, there is a technique to add a parallel processing function to such carry-select type adder/subtractor. FIG. 4 is a view showing the carry-select type adder/subtractor with the parallel processing function in the prior art. In the carry-select type adder/subtractor having the parallel processing function in the prior art shown in FIG. 4, a carry controller 117 is added to the carry-select type adder/subtractor in the prior art which comprises a lower 16-bit adder 111, two 16-bit adders 113, 115 for effecting the upper 16-bit addition, and a carry/SUM selector 119 as its constituent elements.
In the carry-select type adder/subtractor with the parallel processing function in the prior art, in case the 32-bit addition/subtraction is effected, the carry controller 117 sends the carry supplied from the lower 16-bit adder 111 to the carry/SUM selector 119 as it is. In case the 16-bit parallel addition/subtraction is effected, the carry controller 117 always sends the information indicating no carry (e.g., "0") to the carry/SUM selector 119 regardless of the carry supplied from the lower 16-bit adder 111. Therefore, the carry/SUM selector 119 can always select the output data from the upper 16-bit adder which outputs the added result for the case where no carry is supplied from the lower digits. As a result, the 16-bit parallel addition/subtraction can be accomplished.
However, in the case of the adder/subtractor in the prior art, since the controller is added to the upper bit adder and the lower bit adder, additional delay is caused in such added controller when the adder/subtractor is used as one adder circuit. This delay becomes remarkable as the split number is increased. Therefore, such delay becomes a serious issue in the event that a high speed processing is requested.